 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| STV7733 320 output dot-matrix display driver Preliminary Data Features s s High-voltage, row/column driver IC 320, tri-level (high-voltage, medium voltage and ground) power outputs: - capable of operating at 90V, absolute max. - capable of sinking or sourcing 2mA - Hi-Z Logic supply range: 2.5V to 3.3V Slim shape die for COG, COF and TCP solutions Interface: - four dual (2-bit) input serial buses: DBA[1:2], DBB[1:2], DBC[1:2] and DBD[1:2] operating at shift clock frequency of 10MHz, max. - three control inputs: shift clock direction (DIR), chip select (/CS) and data latch (/DL) - two "all output" stage control inputs: AOC1 and AOC2 Power supplies: - high-voltage for power outputs: 90V, max. - logic supply suitable for battery powered applications: 2.5V, min. The STV7733 communicates with the host controller through an 8-bit parallel interface. The input data bus is organized as four, 2 x 80-bit shift registers operating in parallel at a maximum clock frequency of 10MHz. Logic inputs are LVCMOS compatible. The STV7733 is available in bumped die form. Bumped die can be assembled in either a TCP or COG module. Figure 1. Block diagram DIR /CS SCLK VDD s s s DBB1 DBB2 DBC1 DBC2 DBD1 DBD2 Shift register direction DBA1 DBA2 Data decoding VSSL 2 x 80-bit shift register 2 x 80-bit shift register STBTEST 2 x 80-bit shift register OE 2 x 80-bit shift register /DL AOC1 AOC2 POE HVDD MVDD Q1 Q2 Q3 Q4 s 2 x 320-bit latch Q320 Output control VSSS HVDD Tri-level output buffer stage MVDD VSSP Description The STV7733 device is a low-power, controller/driver IC for dot-matrix displays. Data is encoded on two bits to select one of four possible output states: high level, medium level, ground or high impedance (Hi-Z). Inputs AOC1 and AOC2 control the all output stages simultaneously to select one of five possible configurations: high level, medium level, ground, Hi-Z or data through. Except for the data through mode, the configuration selected by AOC1 and AOC2 is applied to all outputs at the same time. VSSP OUT1 OUT2 OUT320 May 2007 Rev 1 1/28 www.st.com 28 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STV7733 Contents 1 2 3 4 5 6 7 8 9 10 11 12 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Die pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AC timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pad dimensions (in microns)/pad positions . . . . . . . . . . . . . . . . . . . . 14 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/28 STV7733 Block diagram 1 Block diagram Figure 2. STV7733 block diagram DIR /CS SCLK VDD DBB1 DBB2 DBC1 DBC2 DBD1 DBD2 Shift register direction DBA1 DBA2 Data decoding VSSL 2 x 80-bit shift register 2 x 80-bit shift register STBTEST 2 x 80-bit shift register OE 2 x 80-bit shift register /DL AOC1 AOC2 POE HVDD MVDD VSSP Q1 Q2 Q3 Q4 2 x 320-bit latch Q320 Output control VSSS HVDD Tri-level output buffer stage MVDD VSSP OUT1 OUT2 OUT320 3/28 Pin description STV7733 2 Pin description Table 1. STV7733 pin description Pin name HVDD MVDD Power supplies VSSP VDD VSSL VSSS DBA[1:2] DBB[1:2] DBC[1:2] Input logic block DBD[1:2] SCLK DIR /CS /DL AOC1 Power output control AOC2 POE Power outputs Test OE I Must be grounded OUT1to OUT320 STBTEST Pin type (I/O) I I I I I I I I I I I I I I I I I O I Pin description Output buffer - high-voltage supply Output buffer - medium voltage supply Output buffer - ground level Logic power supply Logic ground Chip substrate level Input data bus, 2-bit serial interface Input data bus, 2-bit serial interface Input data bus, 2-bit serial interface Input data bus, 2-bit serial interface Data shift clock Shift clock direction Chip select (0 = select, 1 = un-select) Data latch. Shift register data is transferred to the driver outputs at the falling edge of this pulse. "All-output" control (all HVDD, all MVDD, all VSSP, data through mode) selection pin "All-output" control (all HVDD, all MVDD, all VSSP, data through mode) selection pin Power output enable High-voltage power outputs Must be grounded 4/28 STV7733 Die pinout 3 Die pinout Figure 3. Die pinout VSSP VSSP HVDD HVDD MVDD MVDD VSSL VSSS VDD DUMMY DUMMY DUMMY DUMMY OUT1 OUT2 OUT3 OUT4 OUT5 OUT316 OUT317 OUT318 OUT319 OUT320 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VDD VSSS VSSL OE DBD2 DBD1 DBC2 DBC1 DUMMY DUMMY DUMMY DUMMY DBB2 DBB1 DBA2 DBA1 VDD VSSS VSSL CS SCLK DL VSSL VSSS VDD AOC2 AOC1 DUMMY DUMMY POE DIR STBTEST VSSL VSSS VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VSSP VSSP HVDD HVDD MVDD MVDD VSSL VSSS VDD DUMMY DUMMY DUMMY DUMMY Y 0/0 X 5/28 Data bus configuration STV7733 4 Data bus configuration Below, Table 2 describes the position of the first data sampled by the first rising edge of the SCLK clock. For the first configuration described in Table 2, that is, with input DIR = "H", data on the 2-bit bus DBA is sampled by the first SCLK clock pulse and appears on power output OUT1. After 80 clock pulses, data on OUT1 will be shifted to OUT317 - on the high-to-low transition of input /DL. Input /CS is the chip select. Table 2. /CS DIR Data bus configuration SCLK pulse number Input DBA[1:2] DBB[1:2] DBC[1:2] DBD[1:2] DBA[1:2] DBB[1:2] DBC[1:2] DBD[1:2] Position OUT1 OUT OUT OUT OUT OUT OUT OUT OUT 01 02 03 04 320 319 318 317 OUT2 05 06 07 08 316 315 314 313 ... OUT79 OUT80 313 314 315 316 08 07 06 05 317 318 319 320 04 03 02 01 Comment L H Left/Right shift L L Right/Left shift Note: Data is transferred from the shift register to a latch block and then on to power output stages on the falling edge of input /DL, see Figure 2. All output data is stored and held in the latch block on the rising edge of the input /DL, see Figure 2. 6/28 STV7733 Power output stage 5 Power output stage The power output stage is defined by a set of three switches that can select three different output voltages (HVDD, MVDD or VSSP). These switches can also be all opened to configure the output stage in a high impedance (Hi-Z) mode. Depending on the configuration of logic inputs AOC1 and AOC2, the power output stage is configured in either a "data through" mode or a "simultaneous" mode. In the "data through" mode (for AOC1 = AOC2 = "L"), the power output stage converts the 2-bit encoded data that was loaded into the latch stage for each column into a high-voltage level that appears on the output pin. When AOC1 and AOC2 are not both "L", the power outputs can all operate simultaneously - going to VSSP, MVDD or HVDD depending on AOC1 and AOC2 as described below in Table 3. Table 3. DBn[1] X L H H L X X X Power output truth table DBn[2] X L L H H X X X POE L H H H H H H H AOC1 X L L L L H L H AOC2 X L L L L L H H OUTn All Hi-Z Hi-Z VSSP MVDD HVDD All VSSP All MVDD All HVDD Comment (1) (2) (2) (2) (2) (3) (3) (3) 1. With input POE = "L", all power outputs are not active, that is, they are all in Hi-Z. 2. Data through mode: each power output depends on the DBn[1:2] value at the falling edge of input /DL. 3. Output simultaneous mode: all power outputs depend on the "H"/"L" input values for AOC1 and AOC2. 7/28 Absolute maximum ratings STV7733 6 Absolute maximum ratings Table 4. Symbol VDD HVDD MVDD VIN IPOUT VOUT VESD Tjmax Tstg Logic supply range Driver supply range Driver supply range Logic input voltage range Driver output current Power output voltage range ESD susceptibility, Human Body model (100pF discharged through 1.5kohms) Maximum junction temperature Storage temperature range Absolute maximum ratings Parameter Value -0.3, +7 -0.3, +90 -0.3, +HVdd -10 -0.3, VDD + 0.3 5 -0.3, +90 2.0 100 -50, +150 Units V V V V mA V kV C C 8/28 STV7733 Electrical characteristics 7 Electrical characteristics VDD = 3V, HVDD = 70V, MVDD = 35V, VSSP = 0V, VSSL = 0V, VSSS = 0V, Tamb = 25 C, F = 10MHz, unless otherwise specified. Table 5. Symbol Supply VDD IDD IDD1 IDD2 HVDD MVDD IPP VDD supply voltage VDD supply current with no clock, all logic inputs set to either 0V or VDD and all power outputs in Hi-Z VDD dynamic supply current @ clock frequency = 5MHz (data frequency is 2.5MHz) VDD dynamic supply current @ clock frequency = 100kHz (data frequency = 50kHz(1) HVDD supply voltage MVDD supply voltage(2) 2.5 15 15 3 3 0.1 3.3 0.5 80 70 10 V A mA mA V V A Electrical characteristics Parameter Min. Typ. Max. Units HVDD supply current in steady state OUT1 to OUT320 VHPOUTH Power output high level (voltage difference versus HVDD) @ IHPOUTH = -0.5mA and HVDD = 80V - - -10 V Power output medium level (voltage difference versus MVDD) VMPOUTH @ IMPOUTH = + 0.5mA and MVDD = 40V @ IMPOUTL = - 0.5mA and MVDD = 40V VPOUTL Power output low level @ IPOUTL = + 0.5mA Output current from HVDD, MVDD (see Figure 4) 1) HVDD = 80V, MVDD = 40V 2) HVDD = 60V, MVDD = 30V Output current from output to MVDD (Figure 4) 1) HVDD = 80V and MVDD = 40V 2) HVDD = 60V and MVDD = 30V Output current from output to VSSP @ Vdd=2.5V (Figure 4) 1) HVDD = 80V and MVDD = 40V Output current during Hi-Z mode @ VDD = 2.5V, HVDD = 80V and MVDD = 40V - - +10 -10 V V -1.42 -0.7 +1.5 +0.7 +1.5 - - +10 - V mA mA mA mA IPOUTH IPOUTM IPOUTL IHiZ 10 mA A 9/28 Electrical characteristics Table 5. Symbol STV7733 Electrical characteristics (continued) Parameter Min. Typ. Max. Units SCLK, DIR, /CS, DBn[1:2], /DL, AOC1, AOC2 and POE VIH VIL IIH IIL High level input voltage (% of VDD) Low level input voltage (% of VDD) High level input current @ VIH > 0.7 x VDD Low level input current @ VIL = 0V 70 30 5 5 % % A A 1. This measurement is performed during device evaluation - it is not tested on all devices. 2. HVDD must be greater than MVDD under all conditions. Figure 4. MVDD Sink/source current capability test of power outputs HVDD MVDD HVDD MVDD HVDD S1 IPOUTH (-) Out S3 Cp S1 Out Cp S2 S3 S2 S1 Out Cp S3 S2 VSSP IPOUTM (+) VSSP VSSP IPOUTL (+) a) IPOUTH b) IPOUTM c) IPOUTL Reminder: * Current going into the device is a "sinking" current, considered as "positive" * Current coming out of the device is a "sourcing" current, considered as "negative" 10/28 STV7733 AC timing requirements 8 AC timing requirements VDD = 2.5V to 3.3V, Tamb = - 20 to +70C, C input signal edge maximum rise and fall times (tr, tf) = 5ns. Table 6. Symbol tSCLK Data clock period AC timing requirements Parameter Min. 100 40 40 25 25 40 25 25 25 475 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns tWHSCLK Clock pulse duration at high level tWLSCLK Clock pulse duration at low level tSDAT tHDAT tSCS tHCS tHDL tDL tSDL Input data set-up time before low-to-high clock transition Input data hold-time after low-to-high clock transition /CS set-up time before low-to-high clock transition /CS hold-time after low-to-high clock transition /DL hold-time after low-to-high transition of /CS Low level pulse duration /DL set-up time before low-to-high transition of /CS 11/28 AC Timing characteristics STV7733 9 AC Timing characteristics VDD = 3V, HVDD = 70V, MVDD = 35V, VSSP = 0V, VSSL = 0V, VSSS = 0V, Tamb = 25 C, F = 5MHz, Cload = 10pF, unless otherwise specified (VILMAX = 0.3 x VDD, VIHMIN = 0.7 x VDD). Table 7. AC timing characteristics Min. Typ. Max. Units Symbol Parameter Delay between /DL transition and change in level of power output @ VDD = 3V (see Figure 5) 1. OUT1 and OUT320 2. OUT160 and OUT161 Delay between AOC1,2 transitions and change in level of power output (see Figure 5) 1. OUT1 and OUT320 2. OUT160 and OUT161 tPHL2 tPLH2 - 150 500 250 850 ns ns tPLH3M tPLH3H tPHL3M tPHL3L - 150 500 250 850 ns ns Output transition time for one single power output with VDD = 3V, MVDD = 35V and HVDD = 70V (see Figure 5) tR_OUTM Output rise time from VSSP to MVDD tR_OUTH Output rise time from MVDD to HVDD tF_OUTM Output fall time from HVDD to MVDD tF_OUTL Output fall time from MVDD to VSSP - 400 500 800 200 ns ns ns ns 12/28 STV7733 Timing 10 Figure 5. Timing Timing diagram tSCLK Input timing tWHSCLK 50% tSDAT DB (input) 50% tWLSCLK 50% tHDAT 50% 50% 50% SCLK tSCS /CS tHCS 50% Output timing tDL /DL (Latch on falling edge) tSDL tHDL 50% tPHL2 90% 50% OUT(n) 10% tPLH2 3-Steps output timing AOC1,2 50% 50% 50% 50% tPLH3M tPLH3H 95% tPHL3M 95% 55% 45% tPHL3L HVDD MVDD 5% OUT(n) 5% tR_OUTM 55% 45% tR_OUTH tF_OUTM VSSP tF_OUTL 13/28 Pad dimensions (in microns)/pad positions STV7733 11 Pad dimensions (in microns)/pad positions The reference (x=0, y=0) is the center of the die. Bump pad pitch: 68m, minimum (on the power output side of the die). Table 8. Die size Dimension Die size without scribe X Y Die size with scribe X Y 22550 1660 m m 22440 1550 m m Units Pad placement coordinate values correspond to the center of each bump pad center. Number of pads: 404 Table 9. Pad placement and bump dimensions (in microns) Pad placements Lead pad name X OUT320 OUT319 OUT318 OUT317 OUT316 OUT315 OUT314 OUT313 OUT312 OUT311 OUT310 OUT309 OUT308 OUT307 OUT306 OUT305 OUT304 OUT303 -10845.9 -10777.9 -10709.9 -10641.9 -10573.9 -10505.9 -10437.9 -10369.9 -10301.9 -10233.9 -10165.9 -10097.9 -10029.9 -9961.9 -9893.9 -9825.9 -9757.9 -9689.9 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 Bump dimensions(1) 14/28 STV7733 Table 9. Pad dimensions (in microns)/pad positions Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT302 OUT301 OUT300 OUT299 OUT298 OUT297 OUT296 OUT295 OUT294 OUT293 OUT292 OUT291 OUT290 OUT289 OUT288 OUT287 OUT286 OUT285 OUT284 OUT283 OUT282 OUT281 OUT280 OUT279 OUT278 OUT277 OUT276 OUT275 OUT274 OUT273 OUT272 OUT271 OUT270 -9621.9 -9553.9 -9485.9 -9417.9 -9349.9 -9281.9 -9213.9 -9145.9 -9077.9 -9009.9 -8941.9 -8873.9 -8805.9 -8737.9 -8669.9 -8601.9 -8533.9 -8465.9 -8397.9 -8329.9 -8261.9 -8193.9 -8125.9 -8057.9 -7989.9 -7921.9 -7853.9 -7785.9 -7717.9 -7649.9 -7581.9 -7513.9 -7445.9 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 Bump dimensions(1) 15/28 Pad dimensions (in microns)/pad positions Table 9. Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT269 OUT268 OUT267 OUT266 OUT265 OUT264 OUT263 OUT262 OUT261 OUT260 OUT259 OUT258 OUT257 OUT256 OUT255 OUT254 OUT253 OUT252 OUT251 OUT250 OUT249 OUT248 OUT247 OUT246 OUT245 OUT244 OUT243 OUT242 OUT241 OUT240 OUT239 OUT238 OUT237 -7377.9 -7309.9 -7241.9 -7173.9 -7105.9 -7037.9 -6969.9 -6901.9 -6833.9 -6765.9 -6697.9 -6629.9 -6561.9 -6493.9 -6425.9 -6357.9 -6289.9 -6221.9 -6153.9 -6085.9 -6017.9 -5949.9 -5881.9 -5813.9 -5745.9 -5677.9 -5609.9 -5541.9 -5473.9 -5405.9 -5337.9 -5269.9 -5201.9 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 STV7733 Bump dimensions(1) Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 16/28 STV7733 Table 9. Pad dimensions (in microns)/pad positions Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT236 OUT235 OUT234 OUT233 OUT232 OUT231 OUT230 OUT229 OUT228 OUT227 OUT226 OUT225 OUT224 OUT223 OUT222 OUT221 OUT220 OUT219 OUT218 OUT217 OUT216 OUT215 OUT214 OUT213 OUT212 OUT211 OUT210 OUT209 OUT208 OUT207 OUT206 OUT205 OUT204 -5133.9 -5065.9 -4997.9 -4929.9 -4861.9 -4793.9 -4725.9 -4657.9 -4589.9 -4521.9 -4453.9 -4385.9 -4317.9 -4249.9 -4181.9 -4113.9 -4045.9 -3977.9 -3909.9 -3841.9 -3773.9 -3705.9 -3637.9 -3569.9 -3501.9 -3433.9 -3365.9 -3297.9 -3229.9 -3161.9 -3093.9 -3025.9 -2957.9 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 Bump dimensions(1) 17/28 Pad dimensions (in microns)/pad positions Table 9. Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT203 OUT202 OUT201 OUT200 OUT199 OUT198 OUT197 OUT196 OUT195 OUT194 OUT193 OUT192 OUT191 OUT190 OUT189 OUT188 OUT187 OUT186 OUT185 OUT184 OUT183 OUT182 OUT181 OUT180 OUT179 OUT178 OUT177 OUT176 OUT175 OUT174 OUT173 OUT172 OUT171 -2889.9 -2821.9 -2753.9 -2685.9 -2617.9 -2549.9 -2481.9 -2413.9 -2345.9 -2277.9 -2209.9 -2141.9 -2073.9 -2005.9 -1937.9 -1869.9 -1801.9 -1733.9 -1665.9 -1597.9 -1529.9 -1461.9 -1393.9 -1325.9 -1257.9 -1189.9 -1121.9 -1053.9 -985.9 -917.9 -849.9 -781.9 -713.9 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 STV7733 Bump dimensions(1) Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 18/28 STV7733 Table 9. Pad dimensions (in microns)/pad positions Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT170 OUT169 OUT168 OUT167 OUT166 OUT165 OUT164 OUT163 OUT162 OUT161 OUT160 OUT159 OUT158 OUT157 OUT156 OUT155 OUT154 OUT153 OUT152 OUT151 OUT150 OUT149 OUT148 OUT147 OUT146 OUT145 OUT144 OUT143 OUT142 OUT141 OUT140 OUT139 OUT138 -645.9 -577.9 -509.9 -441.9 -373.9 -305.9 -237.9 -169.9 -101.9 -33.9 34.1 102.1 170.1 238.1 306.1 374.1 442.1 510.1 578.1 646.1 714.1 782.1 850.1 918.1 986.1 1054.1 1122.1 1190.1 1258.1 1326.1 1394.1 1462.1 1530.1 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 Bump dimensions(1) 19/28 Pad dimensions (in microns)/pad positions Table 9. Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT137 OUT136 OUT135 OUT134 OUT133 OUT132 OUT131 OUT130 OUT129 OUT128 OUT127 OUT126 OUT125 OUT124 OUT123 OUT122 OUT121 OUT120 OUT119 OUT118 OUT117 OUT116 OUT115 OUT114 OUT113 OUT112 OUT111 OUT110 OUT109 OUT108 OUT107 OUT106 OUT105 1598.1 1666.1 1734.1 1802.1 1870.1 1938.1 2006.1 2074.1 2142.1 2210.1 2278.1 2346.1 2414.1 2482.1 2550.1 2618.1 2686.1 2754.1 2822.1 2890.1 2958.1 3026.1 3094.1 3162.1 3230.1 3298.1 3366.1 3434.1 3502.1 3570.1 3638.1 3706.1 3774.1 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 STV7733 Bump dimensions(1) Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 20/28 STV7733 Table 9. Pad dimensions (in microns)/pad positions Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT104 OUT103 OUT102 OUT101 OUT100 OUT99 OUT98 OUT97 OUT96 OUT95 OUT94 OUT93 OUT92 OUT91 OUT90 OUT89 OUT88 OUT87 OUT86 OUT85 OUT84 OUT83 OUT82 OUT81 OUT80 OUT79 OUT78 OUT77 OUT76 OUT75 OUT74 OUT73 OUT72 3842.1 3910.1 3978.1 4046.1 4114.1 4182.1 4250.1 4318.1 4386.1 4454.1 4522.1 4590.1 4658.1 4726.1 4794.1 4862.1 4930.1 4998.1 5066.1 5134.1 5202.1 5270.1 5338.1 5406.1 5474.1 5542.1 5610.1 5678.1 5746.1 5814.1 5882.1 5950.1 6018.1 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 Bump dimensions(1) 21/28 Pad dimensions (in microns)/pad positions Table 9. Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT71 OUT70 OUT69 OUT68 OUT67 OUT66 OUT65 OUT64 OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39 6086.1 6154.1 6222.1 6290.1 6358.1 6426.1 6494.1 6562.1 6630.1 6698.1 6766.1 6834.1 6902.1 6970.1 7038.1 7106.1 7174.1 7242.1 7310.1 7378.1 7446.1 7514.1 7582.1 7650.1 7718.1 7786.1 7854.1 7922.1 7990.1 8058.1 8126.1 8194.1 8262.1 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 STV7733 Bump dimensions(1) Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 22/28 STV7733 Table 9. Pad dimensions (in microns)/pad positions Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT38 OUT37 OUT36 OUT35 OUT34 OUT33 OUT32 OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 8330.1 8398.1 8466.1 8534.1 8602.1 8670.1 8738.1 8806.1 8874.1 8942.1 9010.1 9078.1 9146.1 9214.1 9282.1 9350.1 9418.1 9486.1 9554.1 9622.1 9690.1 9758.1 9826.1 9894.1 9962.1 10030.1 10098.1 10166.1 10234.1 10302.1 10370.1 10438.1 10506.1 Y 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 600.6 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 Bump dimensions(1) 23/28 Pad dimensions (in microns)/pad positions Table 9. Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X OUT5 OUT4 OUT3 OUT2 OUT1 VSSP VSSP HVDD HVDD MVDD MVDD VSSL VSSS VDD VDD_DUMMY31 VDD_DUMMY30 VDD_DUMMY29 VDD_DUMMY28 VDD_DUMMY27 VDD_DUMMY26 VDD_DUMMY25 VDD_DUMMY24 VDD_DUMMY23 VDD_DUMMY22 VDD_DUMMY21 VDD_DUMMY20 VDD_DUMMY19 VDD_DUMMY18 VDD_DUMMY17 VDD VSSS VSSL OE 10574.1 10642.1 10710.1 10778.1 10846.1 11142.5 11142.5 11142.5 11142.5 11142.5 11142.5 11142.5 11142.5 11142.5 11142.5 11142.5 11142.5 11142.5 10273.7 10001.7 9729.7 9457.7 9185.7 8913.7 8641.7 8369.7 8097.7 7825.7 7276.9 6383.4 6169.1 5897.0 5527.6 Y 600.6 600.6 600.6 600.6 600.6 675.5 607.5 505.5 437.5 335.5 267.5 164.7 -107.5 -328.9 -428.9 -496.9 -598.9 -666.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 X 51.0 51.0 51.0 51.0 51.0 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 STV7733 Bump dimensions(1) Y 73.1 73.1 73.1 73.1 73.1 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 24/28 STV7733 Table 9. Pad dimensions (in microns)/pad positions Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X DBD2 DBD1 DBC2 DBC1 DBC1_DUMMY2 DBC1_DUMMY1 DBB2_DUMMY2 DBB2_DUMMY1 DBB2 DBB1 DBA2 DBA1 VDD VSSS VSSL /CS SCLK /DL VSSL VSSS VDD AOC2 AOC1 AOC1_DUMMY1 POE_DUMMY1 POE DIR STBTEST VSSL VSSS VDD VDD_DUMMY16 VDD_DUMMY15 5157.7 4787.7 4417.8 4047.9 3684.5 2873.6 2049.7 1298.3 380.7 12.6 -355.4 -732.9 -801.0 -1015.3 -1287.4 -2180.9 -2473.8 -2766.7 -2834.8 -3106.9 -3321.2 -3389.2 -3682.1 -4378.2 -5131.9 -5989.1 -6282.0 -6574.9 -6643.0 -6915.1 -7129.4 -7406.3 -7678.3 Y -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 Bump dimensions(1) 25/28 Pad dimensions (in microns)/pad positions Table 9. Pad placement and bump dimensions (in microns) (continued) Pad placements Lead pad name X VDD_DUMMY14 VDD_DUMMY13 VDD_DUMMY12 VDD_DUMMY11 VDD_DUMMY10 VDD_DUMMY9 VDD_DUMMY8 VDD_DUMMY7 VDD_DUMMY6 VDD_DUMMY5 VDD_DUMMY4 VDD_DUMMY3 VDD_DUMMY2 VDD_DUMMY1 VDD VSSS VSSL MVDD MVDD HVDD HVDD VSSP VSSP 1. Tolerance: +/- 3m -7950.3 -8222.3 -8494.3 -8766.3 -9038.3 -9310.3 -9582.3 -9854.3 -10398.2 -10942.2 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 -11142.6 Y -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -700.9 -666.9 -598.9 -496.9 -428.9 -328.9 -107.5 164.7 267.5 335.5 437.5 505.5 607.5 675.5 X 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 STV7733 Bump dimensions(1) Y 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 73.1 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 51.0 26/28 STV7733 Ordering information 12 Ordering information Table 10. Order codes Description Tested and usawn bump wafer (u = die) Gold bumped dice Part numbers STV7733/BMP STV7733/WPB3 13 Revision history Table 11. Date 29-May-2007 Document revision history Revision 1 Initial release Changes 27/28 STV7733 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 28/28 |
Price & Availability of STV7733
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |